The present invention relates to a method of producing a semiconductor integrated circuit device and a semiconductor integrated circuit device, particularly to an effective technique adapted to manufacture of a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory).
In a recent large DRAM of 64 or 256 megabits (Mbits), in forming a contact hole for connecting a bit line or information storage capacitive element to a semiconductor substrate in a space between gate electrodes of a miniaturized memory cell selecting MISFET, the top and sidewalls of the gate electrodes are covered with a silicon nitride film, a silicon oxide film burying the space between the gate electrodes is formed over the silicon nitride film including the space between the gate electrodes and then a contact hole is formed utilizing the different of an etching rate between the silicon oxide film and the silicon nitride film. At that time, the Self Align Contact (SAC) technique is adopted in which a contact hole is opened self-aligningly to the space between the gate electrodes utilizing the different of an etching rate between the silicon oxide film and the silicon nitride film.
As for the SAC technique, it is described in Japanese Patent Laid-Opens No. 135781/1999 and No. 68064/1999, for example. In Japanese Patent Laid-Open No. 135781/1999, it discloses a technique in which a contact hole is opened by the SAC technique and then a sidewall insulating film for protecting an interlayer insulating film is formed in wet etching for removing a natural oxide film that is formed inside the contact hole. Additionally, in Japanese Patent Laid-Open No. 68064/1999, it discloses a technique in which a polycrystalline silicon film is used as an etching stopper in forming a contact hole by the SAC technique and a sidewall comprised of a silicon oxide film is formed on the inner walls of the contact hole to prevent leakage from being generated through the polycrystalline silicon film after opening the contact hole.